The present invention relates generally to ball grid array packages, and more particularly to a thin cavity down ball grid array package based on wirebond technology.
In an integrated circuit, a number of active semiconductor devices are formed on a chip of silicon and interconnected in place by leads to form a complete circuit. As integrated circuit technology has advanced over the years, yields have increased to the point that large arrays of electronic circuits can be produced on a single semiconductor slice. Second and third level interconnections can be used to interconnect the individual circuits as desired and provide bonding pads at the edge of the slice. However, these circuit arrays usually require a large number of external connections. Typical terminal counts in excess of 300 are now required for gate arrays, microprocessors, and very high speed integrated circuit (VHSIC) devices.
In the past, integrated circuit chips have been packaged in a variety of ways. The most common packages are the flatpack, the dual-in-line, the hermetic and plastic chip carrier and the grid array packages, all of which are known to those skilled in the art.
One conventional technique used in the assembling of integrated circuit chip packages is the inclusion of a lead frame which electrically connects the semiconductor die to the outer pins of the package. However, as integrated circuits have become smaller and more complex, the number of leads coming out of the package has increased, even though the package size has remained the same or has decreased. Because of limits within the processing technology of the lead frame, conventional lead frames are no longer able to be used in packages which demand a relatively high pin count which, for example, is 300 or more. New assembling techniques for IC packages have since been developed which are able to accommodate the high pin count demanded by many of the newly manufactured semiconductor devices.
One such technique for assembling integrated circuit chip packages is the so-called TAB for tape automated bonding schemes. The TAB technique is known to those skilled in the art and makes it possible to obtain fine multiple lead patterns with a variety of pattern design variations. Using the TAB technique it is possible to accommodate a significantly larger number of leads than that of the conventional lead frame.
The use of the TAB technique is common in many of today's high lead count IC packages. One such high lead count package is the ball grid array. The ball grid array package is typically a square package with terminals, normally in the form of solder balls, protruding from the bottom of the package only. These terminals are designed to be mounted onto a plurality of bonding pads located on the surface of a printed wiring board (PWB) or other suitable substrate. Two conventional types of ball grid arrays are the TAB ball grid array (TBGA), and the plastic ball grid array (PBGA) .
FIG. 1 is a cross-sectional view of a conventional TAB ball grid array. The die 102 is placed with its active surface facing the TAB tape 110. Laminated on each side of the TAB tape are electrically conductive leads 108 and 112. The die 102 is electrically connected to the inner leads 118 of the TAB tape, the inner leads 118 being part of the upper leads 108. Electrically conducting vias (not shown) connect the upper leads 108 to the lower leads 112 which are, in turn, connected to respective (or corresponding) solder balls 114. This results in each of the terminals of the die 102 being electrically connected to a respective solder ball 114. The active surface of the die 102 is then encapsulated with an encapsulating material 116, which provides environmental and scratch protection to the active surface of the die. In addition, stiffener 104 is bonded via a stiffener adhesive 106 to the TAB tape to give the package structural support. The stiffener 104 is typically made of electrically non-conductive material.
A second type of ball grid array is known as a plastic ball grid array (PBGA). The PBGA is known to those skilled in the art, and although the PBGA is able to accommodate the same relatively high lead count as that of the TBGA, the conventional PBGA is thicker than the conventional TBGA and also offers no means for dissipating heat from the die since the die is fully encapsulated. Despite this disadvantage, both the TAB ball grid array and plastic ball grid array are advantageous over other conventional packages in that both are able to accommodate the greatest number of leads of any of the conventional packages. However, these ball grid array packages are not without their drawbacks.
In general, one drawback associated with conventional ball grid array packages is that the substrate (either TAB tape or PCB material) is required to have two metal layers laminated to it (the metal layers being the conductive patterns 108 and 112 in Fig. 1). This is due to height restrictions created by the solder balls which prevent anything having a thickness greater than that of the solder balls from being mounted on the same side of the package in which the solder balls are located. Since the die is typically as thick as or thicker than the solder balls, attaching the die to the solder ball side of the package would prevent the solder balls from making contact with the printed wiring board (or PC board). In addition, the attachment of the thicker die to the solder ball side of the package will typically result in a thicker package, which is undesirable to many ball grid array package users. These height restrictions therefore require that the die be located on, and thus electrically connected to, one side of the package while the solder balls are located on, and electrically connected to, the opposite side of the package, thereby requiring the use of one metal layer on each side of the package. The necessary inclusion of two metal layers increases the cost of the manufacturing process of the package. In addition, conventional ball grid arrays require electrically conductive vias to connect one side of the metal leads to the other side, further increasing the cost of the manufacturing process.
Another such drawback of conventional ball grid array packages is the cost of the package itself. Referring particularly to conventional TBGA packages, it cost about $100.00 per wafer to form bonding bumps necessary to attach each die formed from the wafer to a respective TAB tape. Since approximately 10 to 20 dies can be produced from one wafer, this results in an increased cost of about $5.00-$10.00 per die using TAB technology. In addition, the length of time required to produce a conventional TBGA prototype is extremely lengthy. A TAB prototype typically takes approximately 16 weeks to complete from the time of design to the time when the part is actually manufactured.
In light of these drawbacks, therefore, one objective of the present invention is to provide a ball grid array package which is as thin as the conventional TAB ball grid array and is able to conduct heat away from the die while at the same time costs less to manufacture than the conventional TBGA and requires less time to produce a prototype. An additional objective of the present invention is to improve the electrical and thermal performance of the ball grid array package.